Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures

Articolo
Data di Pubblicazione:
1997
Citazione:
Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures / Pavan, Paolo; Pellesi, A; Meneghesso, G; Zanoni, E.. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - STAMPA. - 37:(1997), pp. 1561-1564. [10.1016/S0026-2714(97)00109-1]
Abstract:
In this paper, we present results on the influence of the turning on of ESD protection devices on the latch-up sensitivity of 0.35 mu m CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence of guard-rings greatly improves latch-up hardness.
Tipologia CRIS:
Articolo su rivista
Keywords:
CMOS; RELIABILITY; ESD; LATCH-UP
Elenco autori:
Autori di Ateneo:
Link alla scheda completa:
https://iris.unimore.it/handle/11380/8804
Pubblicato in:
MICROELECTRONICS RELIABILITY
Journal