Trap energetic and spatial localization in buried-gate 6H-SiC JFETs by means of numerical device simulation
Articolo
Data di Pubblicazione:
2001
Citazione:
Trap energetic and spatial localization in buried-gate 6H-SiC JFETs by means of numerical device simulation / Verzellesi, Giovanni; G., Meneghesso; A., Cavallini; E., Zanoni. - In: IEEE ELECTRON DEVICE LETTERS. - ISSN 0741-3106. - STAMPA. - 22:12(2001), pp. 579-581. [10.1109/55.974583]
Abstract:
Deep levels with activation energies up to 0.59 eV have been revealed in buried gate, n-channel 6H-silicon carbide JFETs, by means of capacitance- and current-mode deep level transient spectroscopy. Numerical device simulations of the drain-current transients following a gate-to-source voltage step have enabled us to localize the different deep levels both energetically and spatially.
Tipologia CRIS:
Articolo su rivista
Keywords:
Silicon carbide; JFET; deep levels; traps; numerical device simulation.
Elenco autori:
Verzellesi, Giovanni; G., Meneghesso; A., Cavallini; E., Zanoni
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