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Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs

Contributo in Atti di convegno
Data di Pubblicazione:
2012
Citazione:
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs / Abellan, J.L., Fernandez, J., Acacio, M.E., Bertozzi, D., Bortolotti, D., Marongiu, A., Benini, L.. - STAMPA. - (2012), pp. 491-496. (15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 Dresden, deu 12-16 March 2012) [10.1109/DATE.2012.6176519].
Abstract:
Barrier synchronization is a key programming
primitive for shared memory embedded MPSoCs. As the core
count increases, software implementations cannot provide the
needed performance and scalability, thus making hardware
acceleration critical. In this paper we describe an interconnect extension
implemented with standard cells and with a mainstream
industrial toolflow. We show that the area overhead is marginal
with respect to the performance improvements of the resulting
hardware-accelerated barriers.We integrate our HW barrier into
the OpenMP programming model and discuss synchronization
efficiency compared with traditional software implementations.
Tipologia CRIS:
Relazione in Atti di Convegno
Keywords:
embedded systems; shared memory systems; system-on-chip
Elenco autori:
Abellan, J. L.; Fernandez, J.; Acacio, M. E.; Bertozzi, Davide; Bortolotti, Daniele; Marongiu, Andrea; Benini, Luca
Autori di Ateneo:
MARONGIU ANDREA
Link alla scheda completa:
https://iris.unimore.it/handle/11380/1171875
Titolo del libro:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Pubblicato in:
PROCEEDINGS - DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION
Series
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