Memory interference characterization between CPU cores and integrated GPUs in mixed-criticality platforms

Most of today’s mixed criticality platforms feature
Systems on Chip (SoC) where a multi-core CPU complex (the
host) competes with an integrated Graphic Processor Unit (iGPU,
the device) for accessing central memory. The multi-core host
and the iGPU share the same memory controller, which has to
arbitrate data access to both clients through often undisclosed
or non-priority driven mechanisms. Such aspect becomes critical when the iGPU is a high performance massively parallel
computing complex potentially able to saturate the available
DRAM bandwidth of the considered SoC. The contribution of
this paper is to qualitatively analyze and characterize the conflicts
due to parallel accesses to main memory by both CPU cores
and iGPU, so to motivate the need of novel paradigms for
memory centric scheduling mechanisms. We analyzed different
well known and commercially available platforms in order to
estimate variations in throughput and latencies within various
memory access patterns, both at host and device side.