High-k related reliability issues in advanced Non-Volatile Memories

In the last decade, important technology solutions have been proposed to scale down Flash memory devices beyond the 30nm node. The most important innovations are the introduction of charge trapping layer and high- materials in both bottom and top dielectric stacks, which allows reducing both the bottom dielectric thickness and the Program/Erase voltages, while maintaining the P/E performances and (theoretically) without degrading the memory device reliability. Theoretical advantages and reliability issues of these important innovations will be reviewed by addressing physical mechanisms responsible of reliability degradation. In particular, charge trapping layers introduced in place of the poly-silicon FG will be discussed highlighting the reliability consequences of the discrete charge storage. Similarly, theoretical advantages and reliability issues of bottom and top dielectric stacks incorporating high- materials (used mainly also to implement band-gap engineered barriers) will be carefully analyzed, relating high- material properties to memory device performances and reliability.