Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited)

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining theirsimilarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-j stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-j tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.