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  1. Pubblicazioni

Identifying the First Layer to Fail in Dual Layer SiOx/HfSiON Gate Dielectric Stacks

Articolo
Data di Pubblicazione:
2013
Citazione:
Identifying the First Layer to Fail in Dual Layer SiOx/HfSiON Gate Dielectric Stacks / Padovani, Andrea; Nagarajan, Raghavan; Larcher, Luca; Kin Leong, Pey. - In: IEEE ELECTRON DEVICE LETTERS. - ISSN 0741-3106. - ELETTRONICO. - 34:10(2013), pp. 1289-1291. [10.1109/LED.2013.2275182]
Abstract:
We use the thermochemical model of bond breakage to investigate the degradation occurring in dual layer SiOx/HfSiON gate dielectric stacks during low compliance soft breakdown experiments, with the ultimate goal of identifying the first layer that degrades. Time dependent dielectric breakdown (TDDB) experiments reveal that the degradation of conventional SiON and SiOx/HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based breakdown simulations, indicates that the degradation in SiOx/HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multi-layer stack.
Tipologia CRIS:
Articolo su rivista
Keywords:
high-κ dielectric stacks; Interfacial Layer; Thermochemical model; TDDB; Soft breakdown; reliability
Elenco autori:
Padovani, Andrea; Nagarajan, Raghavan; Larcher, Luca; Kin Leong, Pey
Autori di Ateneo:
PADOVANI ANDREA
Link alla scheda completa:
https://iris.unimore.it/handle/11380/965694
Pubblicato in:
IEEE ELECTRON DEVICE LETTERS
Journal
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http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6579645
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