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  1. Research Outputs

Hemt-transistor des normalerweise ausgeschalteten typs mit einem graben, der einen gatebereich enthält und mindestens eine stufe bildet, sowie entsprechendes herstellungsverfahren

Patent
Publication Date:
2016
Short description:
Hemt-transistor des normalerweise ausgeschalteten typs mit einem graben, der einen gatebereich enthält und mindestens eine stufe bildet, sowie entsprechendes herstellungsverfahren / Iucolano, Ferdinando; Patti, Alfonso; Chini, Alessandro. - (2016 May 25).
abstract:
A normally-off type HEMT transistor comprising: a semiconductor heterostructure (4, 6, 200) having at least a first layer (4) and a second layer (6), the second layer being on top of the first layer is arranged; a trench (15) extending through the second layer and a portion of the first layer; a gate region (10) of conductive material extending into the trench; and a dielectric region (18) extending into the trench, covering the gate region and in contact with the semiconductor heterostructure. A portion of the trench is bounded laterally by a lateral structure (LS) forming at least a first stage (Pb1, P11, Pb2). The semiconductor heterostructure forms a first edge (E1) and a second edge (E2) of the first stage, wherein the first edge is formed by the first layer.
Iris type:
Brevetto
Keywords:
HEMT, Power FET, WBG Semiconductors
List of contributors:
Iucolano, Ferdinando; Patti, Alfonso; Chini, Alessandro
Authors of the University:
CHINI Alessandro
Handle:
https://iris.unimore.it/handle/11380/1190102
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