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  1. Research Outputs

Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces

Academic Article
Publication Date:
2025
Short description:
Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces / Cortiula, Alessio; Menin, Davide; Bandiziol, Andrea; Driussi, Francesco; Palestri, Pierpaolo. - In: ELECTRONICS. - ISSN 2079-9292. - 14:10(2025), pp. 1-14. [10.3390/electronics14101979]
Iris type:
Articolo su rivista
Keywords:
clock and data recovery; high-speed I/O; jitter tolerance; PAM-4;
List of contributors:
Cortiula, Alessio; Menin, Davide; Bandiziol, Andrea; Driussi, Francesco; Palestri, Pierpaolo
Authors of the University:
PALESTRI Pierpaolo
Handle:
https://iris.unimore.it/handle/11380/1378148
Full Text:
https://iris.unimore.it//retrieve/handle/11380/1378148/895702/CortiulaMDPI_2025.pdf
Published in:
ELECTRONICS
Journal
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