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  1. Research Outputs

Normally-off heterojunction integrated device and method for manufacturing an integrated device

Patent
Publication Date:
2024
Short description:
Normally-off heterojunction integrated device and method for manufacturing an integrated device / Miccoli, Cristina; Iucolano, Ferdinando; Tringali, Cristina; Eloisa Castagna, Maria; Chini, Alessandro. - (2024 Mar 05).
abstract:
An integrated power device includes a heterostructure, having a channel layer and a barrier layer, a source contact, a drain contact, and a gate region, arranged on the barrier layer between the source contact and the drain contact. An insulating field structure is arranged on the barrier layer between the gate region and the drain contact. A field plate extends over the insulating field structure. The insulating field structure includes a first dielectric region made of a first dielectric material on the barrier layer and a second dielectric region made of a second dielectric material, selectively etchable with respect to the first dielectric material on the first dielectric region. On a side of the insulating field structure towards the gate region, the field plate is in contact with the first dielectric region.
Iris type:
Brevetto
Keywords:
HEMT, Power FET, WBG Semiconductors
List of contributors:
Miccoli, Cristina; Iucolano, Ferdinando; Tringali, Cristina; Eloisa Castagna, Maria; Chini, Alessandro
Authors of the University:
CHINI Alessandro
Handle:
https://iris.unimore.it/handle/11380/1400056
Full Text:
https://iris.unimore.it//retrieve/handle/11380/1400056/961112/US20240313102A1.pdf
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