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Performance Benchmarking and Effective Channel Length for Nanoscale InAs, In0.53Ga0.47As, and sSi n-MOSFETs

Articolo
Data di Pubblicazione:
2014
Citazione:
Performance Benchmarking and Effective Channel Length for Nanoscale InAs, In0.53Ga0.47As, and sSi n-MOSFETs / Lizzit, Daniel; Esseni, David; Palestri, Pierpaolo; Osgnach, Patrik; Selmi, Luca. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 61:6(2014), pp. 2027-2034. [10.1109/TED.2014.2315919]
Abstract:
Thanks to the high electron velocities, III–V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As, and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III–V and Si nanoscale MOSFETs with a given gate length (LG) may have a quite different effective channel length (Leff); 2) the difference in Leff provides a useful insight to interpret the performance comparison of III–V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III–V MOSFETs.
Tipologia CRIS:
Articolo su rivista
Keywords:
III–V; device simulation; drain-induced barrier lowering (DIBL); effective channel length; Monte Carlo; strained Si (sSi); subthreshold swing (SS)
Elenco autori:
Lizzit, Daniel; Esseni, David; Palestri, Pierpaolo; Osgnach, Patrik; Selmi, Luca
Autori di Ateneo:
PALESTRI Pierpaolo
SELMI LUCA
Link alla scheda completa:
https://iris.unimore.it/handle/11380/1163219
Pubblicato in:
IEEE TRANSACTIONS ON ELECTRON DEVICES
Journal
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