Engineering Barrier and Buffer Layers in InGaAs Quantum-Well MOSFETs

Properties of InGaAs buried-channel quantum-well MOSFETs affected by the barrier and buffer layers are analyzed by numerical simulations to assist device engineering and optimization. The interplay between the charge-neutrality level position at the barrier/dielectric interface and conduction band discontinuity at the barrier/channel interface is shown to critically impact the achievement of an enhancement-mode device with full turn-on. A p-doped buffer is found to be a more suitable option than the standard unintentionally doped buffers to control short-channel effects.