Skip to Main Content (Press Enter)

Logo UNIMORE
  • ×
  • Home
  • Degree programmes
  • Modules
  • Jobs
  • People
  • Research Outputs
  • Academic units
  • Third Mission
  • Projects
  • Skills

UNI-FIND
Logo UNIMORE

|

UNI-FIND

unimore.it
  • ×
  • Home
  • Degree programmes
  • Modules
  • Jobs
  • People
  • Research Outputs
  • Academic units
  • Third Mission
  • Projects
  • Skills
  1. Research Outputs

A model of the stress induced leakage current in gate oxides

Academic Article
Publication Date:
2001
Short description:
A model of the stress induced leakage current in gate oxides / Larcher, Luca; A., Paccagnella; G., Ghidini. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 48:2(2001), pp. 285-288. [10.1109/16.902728]
abstract:
A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations pf the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress.
Iris type:
Articolo su rivista
Keywords:
Flash memory; Stress Induced Leakage Current; compact modeling; solid-state device simulation
List of contributors:
Larcher, Luca; A., Paccagnella; G., Ghidini
Handle:
https://iris.unimore.it/handle/11380/305554
Published in:
IEEE TRANSACTIONS ON ELECTRON DEVICES
Journal
  • Use of cookies

Powered by VIVO | Designed by Cineca | 26.4.5.0