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  1. Pubblicazioni

A model of the stress induced leakage current in gate oxides

Articolo
Data di Pubblicazione:
2001
Citazione:
A model of the stress induced leakage current in gate oxides / Larcher, Luca; A., Paccagnella; G., Ghidini. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 48:2(2001), pp. 285-288. [10.1109/16.902728]
Abstract:
A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations pf the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress.
Tipologia CRIS:
Articolo su rivista
Keywords:
Flash memory; Stress Induced Leakage Current; compact modeling; solid-state device simulation
Elenco autori:
Larcher, Luca; A., Paccagnella; G., Ghidini
Link alla scheda completa:
https://iris.unimore.it/handle/11380/305554
Pubblicato in:
IEEE TRANSACTIONS ON ELECTRON DEVICES
Journal
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