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  1. Research Outputs

A new model of gate capacitance as a simple tool to extract MOS parameters

Academic Article
Publication Date:
2001
Short description:
A new model of gate capacitance as a simple tool to extract MOS parameters / Larcher, Luca; Pavan, Paolo; F., Pellizzer; G., Ghidini. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 48:5(2001), pp. 935-945. [10.1109/16.918242]
abstract:
This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide held, surface potentials at the Si/SiO2 and at the poly-Si/SiO2 interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors, The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n+/n+ MOS capacitor from CV curves is proposed.
Iris type:
Articolo su rivista
Keywords:
Capacitance measurements; compact modeling; electrical characterization; MOSFET
List of contributors:
Larcher, Luca; Pavan, Paolo; F., Pellizzer; G., Ghidini
Authors of the University:
PAVAN Paolo
Handle:
https://iris.unimore.it/handle/11380/306048
Published in:
IEEE TRANSACTIONS ON ELECTRON DEVICES
Journal
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