Three dimensional effects in dynamically triggered CMOS latch-up

An analysis of three-dimensional (3-D) effects in CMOS latchup under dynamic conditions that expands on previous work limited to steady state is presented. Measurements of the minimum duration of voltage pulses and the ramp slew rate needed to induce latchup and have been performed on devices of different widths and layouts, and the latchup susceptibility to transient stimuli has been found to depend on the device dimensions and geometry. By means of simple analytical models it is shown that such a dependence originates from the nonideal scaling of the distributed resistances and capacitances due to the 3-D nature of the structure terminating regions