Correlating Interface and Border Traps With Distinctive Features of C–V Curves in Vertical Al$_{\text{2}}$O$_{\text{3}}$/GaN MOS Capacitors

In this article, we present an analysis of the correlation between interface traps (ITs) and border traps (BTs) on distinctive features of C – V curves in vertical Al 2 O 3 /gallium-nitride (GaN) MOS capacitors. First, pulsed C – V curves were characterized during the application of quiescent gate bias stresses of different magnitudes and signs. This characterization revealed four main distinctive features: 1) rightward rigid shift; 2) leftward rigid shift; 3) decrease of the Δ C – Δ V slope; and 4) formation of a hump in a gate bias range before the accumulation of electrons at the oxide/semiconductor interface. By means of a combined experimental/simulation analysis, these features were univocally attributed to specific ITs or BTs in the overall trap distribution. The simulation-aided analysis enhances the physical understanding of the C – V curves features and increases the dependability of the adopted IT measurement technique, allowing for a more rapid process optimization and device technology development.