Energy-efficient logic-in-memory I-bit full adder enabled by a physics-based RRAM compact model

In this work, we explore the RRAM-based IMPLY logic by means of circuit simulations. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the AC and the DC behavior, accounting for the intrinsic variability of the resistive states and the logic state degradation. A new implementation of a 1-bit full adder with unique properties for low-power circuits is proposed, and its performance in terms of energy consumption and execution time is evaluated by simulations. Results are compared against recent experiments, demonstrating a good agreement and indicating the direction for further improvement.